Highly Efficient AES Core for Virtex-5 FPGAs
In a joint project Saar, Christof and I built an AES implementation which is mainly based on the BlockRAM and DSP units present in Xilinx's Virtex-5 FPGA devices. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s on this platform when processing two 128 bit inputs. This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs. Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs.
The complete source code for these designs is made publicly available for use in further research and for replicating our results.