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Highly Efficient AES Core for Virtex-5 FPGAs

Highly Efficient AES Core for Virtex-5 FPGAs
aes_dsp.zip
Version:
1.0
Author:
Saar Drimer, Tim Güneysu, Christof Paar
Date:
09 April 2015

In a joint project Saar, Christof and I built an AES implementation which is mainly based on the BlockRAM and DSP units present in Xilinx's Virtex-5 FPGA devices. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s on this platform when processing two 128 bit inputs. This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs. Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs.

The complete source code for these designs is made publicly available for use in further research and for replicating our results.

 

License Agreement

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Copyright © 2015 by Tim Güneysu. All rights reserved.

Contact Tim Güneysu for comments & questions.
This program is free software; You may use it or parts of it or modify it under the following terms:

(1) Usage and/or redistribution and/or modification of the software or parts of the software is permitted for non-commercial use only.

(2a) If this software or parts are used as part of a new software, you must license the entire work, as a whole, under this License to anyone who comes into possession of a copy. This License will therefore apply, to the whole of the work, and all its parts, regardless of how they are packaged.

(2b) You may expand this license by your own license. In this case this license still applies to the software as mentioned in (2a) and must not be changed. The expansion must be clearly recognizable as such. In any case of collision between the license and the expansion the license is superior to the expansion.

(3) If this software or parts are used as part of a new software, you must provide equivalent access to the source code of the entire work, as a whole, to anyone who comes into possession of a copy, in the same way through the same place at no further charge, as for the binary version.

(4) This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

(5) These notices must be retained in any copies of any part of this documentation and/or software.

(6) If this software is used credit must be given to the "Hardware Security Group of Ruhr-Universitaet Bochum, Germany" as the authors of the parts of the software used. This can be in the form of a textual message at program startup or at *beginning* of the documentation (online or textual) provided with the package.

If you are interested in a commercial use please contact me (Tim Güneysu).
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